SAVONA: Design, Specification & Verification of Embedded Systems

Application area

SAVONA is a powerful tool used for designing, specifying and verifying embedded systems (hardware & software). It combines model-based development methods with design-by-contract, enabling validation and verification of the system’s architecture at an early stage of development. In agile environments, SAVONA allows to quickly analyze the influence of requirement changes on the system´s integrity. In safety-relevant environments, required safety proofs in can be integrated at an early stage. System architecture models are graphically created with an intuitive user Interface in SysML. Well readable, semi-formal contracts can be easily assigned to the specific system architecture and automatically validated through model checking.

SAVONA is now available as a free pre-release version (Download SAVONA 1.0.0.) The full version comes Q3 / 2018 on the market.

Functions at a glance

  • Graphical design of system architecture (SysML IBD) of embedded systems (hardware & software)
  • Tool-supported specification of system behavior using constraint-natural-language
  • Automatic validation and verification of the system´s architecture based on models and specifications
  • Automatic generation of system documentation with model & specification artifacts
  • Multiple interfaces, such as IBM DOORS, HP ALM

Benefits of SAVONA

  • Validation and verification of the system´s architecture to detect and fix errors during the design phase
  • Use of constraint-natural-language allows an easy access to formal verification and enables a higher quality of system specifications
  • Automated requirement tracing on the incrementally refined system architecture
  • Adapted to the requirements of agile and safety relevant development
  • Universally applicable in embedded development projects for automotive, aerospace or industry

Service & information

Technical Support


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